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An efficient microcode compiler for application specific DSP processors

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4 Author(s)
Goossens, G. ; Interuniv. Micro-Electron. Center, Leuven, Belgium ; Rabaey, J. ; Vandewalle, J. ; De Man, H.

A computer program for microcode compilation for custom digital signal processors is presented. This tool is part of the CATHEDRAL II silicon compiler. The following optimization problems are highlighted: scheduling, hardware assignment, and loop folding. Efficient techniques to solve these problems are developed. This allows for the automatic synthesis of processor architectures which simultaneously exploit pipelining and parallelism. A demonstrator design is presented

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:9 ,  Issue: 9 )