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An optimal fault-tolerant design approach for array processors

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3 Author(s)
Zhang, C.N. ; Dept. of Comput. Sci., Regina Univ., Sask., Canada ; Bachtiar, T.M. ; Chou, W.K.

A systematic approach for designing fault tolerant systolic array using space/time redundancy is proposed. The approach is based upon a fault tolerant mapping theory which relates space-time mapping and concurrent error detection techniques. By this design approach, the resulting systolic array is fault tolerant and optimal. Besides, it has the capability to compute more problem instances simultaneously without extra cost

Published in:

Parallel and Distributed Systems, 1994. International Conference on

Date of Conference:

19-22 Dec 1994