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Modeling testing-strategies for yield enhancement of multichip module systems

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3 Author(s)
Sungsoo Kim ; Ajou Univ., Suwon, South Korea ; N. Park ; P. Lombardi

This paper presents analytic models for evaluating test-strategy (TS) for yield enhancement of systems manufactured using fault-tolerant (FTol) multichip modules (MCM) for massively parallel computing. Several methods for testing FTol-MCM have been proposed, but there is little analytic evaluation. This paper uses a novel Markov model to compute the yield. Unlike a previous method which uses a binomial distribution, our TS can use intermediate tests (Intmed-T). This paper shows an efficient TS with a modest level of redundancy to achieve 100% first-pass MCM yield for a particular system. Two methods using Intmed-T for FTol-MCM are proposed and analyzed. When Intmed-T are used for all mounted chips, FTol-MCM with more than a few chips require known-good chips of at least a 99.9% probability-good for achieving a high yield. An efficient TS with a modest level of redundancy can exist for achieving a 100% first-pass MCM yield for a particular system. A yield-analysis model using the least recently tested (LRT) TS in this paper provides a very good figure-of-merit due to its cost, delivery, number of tests, and reliability benefits for current technology. Extensive parametric results for the analysis show that LRT-TS can be applied to calculate the overall yield for FTol-MCM more accurately and efficiently, thereby improving the system reliability

Published in:

IEEE Transactions on Reliability  (Volume:46 ,  Issue: 2 )