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Through-silicon via (TSV) technology, an enabler for 3D ICs, has evolved, enabling thinner and shorter TSVs within substantially thinned wafers to achieve faster interconnects, large bandwidth density, and low power consumption. Yet, heat dissipation in 3D ICs becomes more and more challenging, especially in applications that require stacking of multiple processor and memory chips. Microfluidic cooling has been proposed as a solution to reject heat from 3D stacks that contain processor chips. However, current liquid cooling technology inevitably increases the wafer thickness, which is contrary to TSV technology trend. To date, little work has been done to optimize heat sink design to benefit TSV performance, and no attempt has been made to analyze the corresponding impact of a particular heat sink design on the performance of the electrical TSVs. A heat sink design without consideration of TSV performance can greatly diminish the advantages of 3D ICs. This paper presents a holistic cooling solution for 3D ICs, which not only meets thermal requirements, but also minimizes TSV parasitics that impact latency, bandwidth density, and power consumption. This paper will report: a) the design of a 3D-centric heat sink, b) the fabrication of the heat sink and associated high aspect ratio integrated TSVs, c) the thermal testing of the liquid-cooled heat sink and comparison to air-cooled heat sink, and d) the impact of the heat sink geometry on TSV capacitance.