By Topic

Modeling of electromigration in through-silicon-via based 3D IC

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Pak, J.S. ; ECE Dept., Univ. of Texas at Austin, Austin, TX, USA ; Pathak, M. ; Sung Kyu Lim ; Pan, D.Z.

Electromigration (EM) is a critical problem for interconnect reliability of modern IC design, especially as the feature size becomes smaller. In 3D IC technology, the EM problem becomes more severe due to drastic dimension mismatches between metal wires, through-silicon-vias (TSVs), and landing pads. Meanwhile, the thermo-mechanical stress due to TSV can further interact with EM and shorten the lifetime of the structure. However, there is very little study on EM issues with respect to TSV for 3D ICs. In this paper, we perform detailed and systematic studies on: (1) EM lifetime modeling of TSV structure, (2) impact of TSV stress on EM lifetime of BEOL wires, and (3) EM-robust design guidelines for TSV-based 3D ICs. Our results show EM-induced lifetime of TSV structure and neighboring wire largely depend on the TSV-induced stress. Also, lifetime of a wire can vary significantly depending on the relative position with the nearby TSV.

Published in:

Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st

Date of Conference:

May 31 2011-June 3 2011