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Impact of slurry in Cu CMP (chemical mechanical polishing) on Cu topography of Through Silicon Vias (TSVs), re-distribution layers, and Cu exposure

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14 Author(s)
J. C. Chen ; Electronics and Optoelectronics Research Labs, Industrial Technology Research Institute, Rm. 256, Bldg. 17, No. 195, Sec. 4, Chung Hsing Road, Chutung, Hsinchu 310, Taiwan ; P. J. Tzeng ; S. C. Chen ; C. Y. Wu
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In this study, the optimization of Cu CMP performance (dishing) for removing thick Cu plating overburden due to Cu plating for deep TSVs in a 300mm wafer is investigated. Also, backside isolation oxide CMP for TSV Cu exposure is discussed. In order to obtain a minimum Cu dishing on the TSV region, a proper selection of Cu slurries is proposed for the current two-step Cu polishing process. The bulk of Cu is removed with the slurry of high Cu removal rate at the first step and the Cu surface is planarized with the slurry of high Cu passivation capability at the second step. The Cu dishing can be improved up to 97% for the 10μm-diameter TSVs on a 300mm wafer. The dishing/erosion of the metal/oxide can be reduced with respect to a correspondingly-optimized Cu plating overburden for TSVs and RDLs. Cu metal dishing can be drastically reduced once the Cu overburdens are increased to a critical thickness. For backside isolation oxide CMP for TSV Cu exposure, the results show that the Cu studs of TSVs with a bigger via size still keep in a plateau-like shape after CMP.

Published in:

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

Date of Conference:

May 31 2011-June 3 2011