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Through-silicon via (TSV), being one of the key enabling technologies for 3D system integration, is being used to interconnect 3D vertically stacked devices, such as logic, memory, sensors, and actuators that are fabricated on separate wafers and then interconnected by either wafer-to-wafer or chip-to-wafer methods. However, thermo-mechanical analyses on TSVs are limited, and most of the existing studies focus on the thermo-mechanical analysis of TSVs in a freestanding wafer, rather than in an integrated package. In this paper, three-dimensional thermo-mechanical finite-element models have been built to analyze the stress/strain distribution in a 3D integrated package which contains stacked dice with TSVs, inter-chip microbumps, overmold, and underfilled solder bumps, and an organic substrate. Models show that the stresses in the TSV under packaging configuration could be generally lower than the stresses in the TSV in a free-standing wafer. Also, the models show that the high-strain region switches from TSV corners to microbumps.