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Development of wafer level underfill materials and assembly processes for fine pitch Pb-free solder flip chip packaging

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5 Author(s)
Nah, J. ; IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA ; Gaynes, M.A. ; Feger, C. ; Katsurayama, S.
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We developed a latent curing, low outgassing wafer level underfill (WLUF) material and applied fast temperature ramping to achieve 100% electrically and metallurgically good flip chip solder joints. Also, void formation within the underfill material during the bonding process was minimized. Subsequently, these voids were virtually eliminated during a post cure process of the WLUF material which uses pulsed amplitude pressure. A WLUF with 60% (weight) filler was applied by spin coating onto a wafer with Pb-free solder bumps. Following B-stage curing at 90°C, the thickness was measured to be 20 microns over the solder bump height. In the B-staged state, this WLUF is stable at room temperature for several weeks. After the wafer was diced into chips, a chip was aligned and joined to a substrate with an optimized heating and cooling cycle. This WLUF assembly process has been evaluated using a flip chip test vehicle with 150 micron pitch and 3,300 area array solder bumps. The chip bumps were SnAg solder and the pre-solder on the substrate was SnAgCu. The size of the test chip was 9 × 13 mm and the test substrate was 42.5 × 42.5 mm. The test chip and substrate were designed to allow both two and four wire contact resistance measurements of the electrical interconnect structures. We successfully demonstrated 100% electrically and metallurgically good Pb-free joints. Voids inside the WLUF after flip chip bonding were decreased significantly using the pulsed amplitude pressure, post cure process. Scanning acoustic microscopy (SAM) analysis showed nearly void-free underfill bonding. After JEDEC level three preconditioning, environmental stress testing was completed and included 1000 deep thermal cycles of -55 to 125°C; 1000 hrs at 85C/85% temperature and humidity; and 1000 hrs of 150°C high temperature storage. Contact resistance measurements were made at time zero, after preconditioning and every 250 cycles or hours of environmental str- - ess. The contact resistance measurements were stable on all parts. Detailed material and process development, and reliability test results are described in this paper.

Published in:

Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st

Date of Conference:

May 31 2011-June 3 2011