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Hybrid integration of silicon nanophotonics with 40nm-CMOS VLSI drivers and receivers

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19 Author(s)
Hiren D. Thacker ; Oracle Labs, San Diego, CA, Oracle Labs, 9515 Towne Centre Drive, San Diego, CA 92121 ; Ivan Shubin ; Ying Luo ; Joannes Costa
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Oracle's scalable hybrid integration technology platform enables continuing improvements in performance and energy efficiency of photonic bridge chips by leveraging advanced CMOS technologies with maximum flexibility, which is critical for developing ultralow power high-performance photonic interconnects for future computing systems. Herein, we report on our second generation of photonic bridge chips comprising electronic drivers and receivers built in 40 nm bulk CMOS technology attached to nanophotonic devices, fabricated using SOI-photonic and 130 nm SOI-CMOS photonic technologies. Hybrid integration by flip-chip bonding is enabled by microsolder bump interconnects scaled down from our previous generation effort and fabricated on singulated dies by a novel batch processing technique based on component embedding. Generation-on-generation, the hybrid integrated Tx and Rx bridge chips achieved 2.3× and 1.7× improvement in energy efficiency, respectively, while operating at 2× the datarate (10 Gbps).

Published in:

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

Date of Conference:

May 31 2011-June 3 2011