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Exploration of the design space of wafer level packaging through numerical simulation

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6 Author(s)
Zhongping Bao ; Qualcomm Inc., San Diego, CA, USA ; Burrell, J. ; Keser, B. ; Yadav, P.
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Wafer Level Packaging (WLP) refers to the technology that integrated circuits are packaged at wafer level and after singulation such chips are then connected directly to the PCB through individual solder balls using standard SMT process [1,2,3,4]. WLP enables true chip size packages with other advantages including lower profile, lighter weight, better thermal and electrical performance, and lower cost. Since the devices are packaged at the wafer level, assembly of discrete chips, interconnects such as bumps or wire bonds, and substrates are eliminated. In this paper we carried out empirical and numerical studies of solder joint reliability under thermal cycling for ball-on-redistribution layer (RDL) type WLP. Test vehicles (TV) covering large range of die size as well die aspect ratio are designed and tested for board level reliability under thermal cycling. Large variations in bump layout and overall ball density are also considered in the TVs. Experimental setup monitors both corner and non-corner ball failures and reports the 1st plus 1% failure. 3-D finite element modeling is performed to investigate the effects of die size, and ball pattern on board level solder joint reliability under thermal cycling. Hyperbolic sine law proposed in [5,11] is assumed for modeling solder creep behavior. Thermal fatigue life model presented in [6,7] is implemented here for establishing correlation between empirical data and simulation results. By including realistic boundary conditions and refined mesh in observed solder failure region, the simulation achieves excellent correlation and prediction compared to empirical data, within 12% error in terms of 1st cycle to failure. The effect of die size, as well as die aspect ratio is examined. It is found that DNP shows a strong linear correlation to the metric, ISED - Inelastic Strain Energy Density, extracted in solder region from the numerical model. Since a power law between ISED and 1st failure in- - cycles is assumed for life prediction, a similar empirical formula between die size and 1st failure in cycles can then be defined based on modeling data. Effects of customized board and boundary conditions on solder joint reliability are also included. The paper is prepared to the best knowledge of authors and those statements do not necessarily reflect opinions of Qualcomm Inc or any other parties. Some data shared in this paper is normalized such that no commercial confidential information is published.

Published in:

Electronic Components and Technology Conference (ECTC), 2011 IEEE 61st

Date of Conference:

May 31 2011-June 3 2011