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Process integration and reliability test for 3D chip stacking with thin wafer handling technology

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9 Author(s)
H. H. Chang ; Electronics and Optoelectronics Research Laboratories (EOL), Industrial Technology Research Institute (ITRI), Taiwan ; J. H. Huang ; C. W. Chiang ; Z. C. Hsiao
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In this study, a three-dimensional (3D) integrated circuit (IC) chip stacking structure with a through-silicon via (TSV) is proposed. A high aspect ratio, void-free Cu electro-plating technology was achieved through super filling. The aspect ratio of the TSV was larger than eight. For chip stacking, Cu/Sn micro bumps with diameters less than 20 μm were used. Solder shape prediction using surface evolver showed good correlation with experiment results within a 2.5% error. Thin wafer handling technology with thermal plastic material was also adopted in this paper. The outgassing issue for silicon dioxide (SiO2) was improved dramatically when an additional silicon nitride (Si3N4) film deposition was made. Using the slide-off method with thermal plastic thin wafer handling material, an eight-inch wafer with a thickness of less than 50 μm was processed. After the die-saw process, ten chips could be stacked using the die bonder. Thermal cycling reliability test was also conducted with the temperature ranging from -55 to 125°C. The reliability life for the proposed structure was 3,777 cycles from the Weibull plot. The average resistance for one interconnection was less than 50 mΩ. A 3D finite element model was also established in this study. The CTE mismatch between the polyimide and the silicon resulted in warpage. The simulation results showed that the maximum von Mises stress occurred at the corner of the TSV which could lead to a failure mode called “copper pumping.” For the von Mises stress in the micro bump, the maximum value occurred between the inter-metallic compound and the substrate copper pad. From the cross-sectional SEM image of the failed sample after thermal cycling test, the failure mode had good correlation with the simulation results. Equivalent plastic strain was around 0.11% in this simulation. As both silicon substrate and silicon chips were used in this study, a small eq- - uivalent plastic strain is expected.

Published in:

2011 IEEE 61st Electronic Components and Technology Conference (ECTC)

Date of Conference:

May 31 2011-June 3 2011