Skip to Main Content
We have developed a new system-in-package (SiP) called a “System in Wafer-Level Package” (SiWLP). It is fabricated using “RDL-first” technology for fan-out wafer-level-packages (FO-WLPs) and provides high chip-I/O density, design flexibility, and package miniaturization. We developed this SiWLP by using multilayer RDLs and evaluated its unique packaging processes. We achieved high-throughput fabrication by using die-to-wafer (D2W) bonding with fine-pitch reflow soldering and simultaneous molding/underfilling at the wafer level.