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Subthreshold Characteristics of MOS Transistors With  \hbox {CeO}_{2}/\hbox {La}_{2}\hbox {O}_{3} Stacked Gate Dielectric

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4 Author(s)
Hei Wong ; Department of Electronic Engineering, City University of Hong Kong, Kowloon , Hong Kong ; B. L. Yang ; K. Kakushima ; Hiroshi Iwai

This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3/Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements.

Published in:

IEEE Electron Device Letters  (Volume:32 ,  Issue: 8 )