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Browse Journals & Magazines > Electron Device Letters, IEEE ...> Volume:32 Issue:8 Help

Subthreshold Characteristics of MOS Transistors With \hbox {CeO}_{2}/\hbox {La}_{2}\hbox {O}_{3} Stacked Gate Dielectric

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4 Author(s)
Hei Wong ; Dept. of Electron. Eng., City Univ. of Hong Kong, Kowloon, China ; Yang, B.L. ; Kakushima, K. ; Iwai, H.

This letter reports the subthreshold characteristics of MOS transistors with the novel CeO2/La2O3 stacked gate dielectric. We found that the top CeO2 capping layer does not only improve the bulk properties of La2O3 by reducing the oxygen vacancies as a result of the reduction reaction of CeO2 but also reduces the La2O3/Si interface trap pronouncedly. We further identify the energy level of the interface traps by conducting temperature-dependent subthreshold slope measurements.

Published in:
Electron Device Letters, IEEE  (Volume:32 ,  Issue: 8 )

Date of Publication: Aug. 2011

Page(s):
1002 - 1004
ISSN :
0741-3106
INSPEC Accession Number:
12136026
Digital Object Identifier :
10.1109/LED.2011.2157799
Product Type:
Journals & Magazines
Date of Publication :
20 June 2011
Date of Current Version :
25 July 2011
Issue Date :
Aug. 2011
Sponsored by :
IEEE Electron Devices Society

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