By Topic

Wet etch step modelling to help shallow trench isolation module control

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
A. Roussy ; EMSE-CMP Georges Charpak, 880 Avenue de Mimet, 13541, Gardanne France ; M. Gedion ; N. Crousier ; J. Pinaton
more authors

We propose a method to model the wet etch process within the Shallow Trench Isolation (STI) module in the CMOS technology. To model a process is the first step in the design of a run to run system, in order to reduce for example the lot to lot variability (a lot equals 25 wafers). The developed predictive model is based on a Design Of Experiments (DOE).

Published in:

2011 IEEE/SEMI Advanced Semiconductor Manufacturing Conference

Date of Conference:

16-18 May 2011