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Wet etch step modelling to help shallow trench isolation module control

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5 Author(s)
Roussy, A. ; EMSE-CMP Georges Charpak, Gardanne, France ; Gedion, M. ; Crousier, N. ; Pinaton, J.
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We propose a method to model the wet etch process within the Shallow Trench Isolation (STI) module in the CMOS technology. To model a process is the first step in the design of a run to run system, in order to reduce for example the lot to lot variability (a lot equals 25 wafers). The developed predictive model is based on a Design Of Experiments (DOE).

Published in:

Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI

Date of Conference:

16-18 May 2011

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