Referenced Items are not available for this document.
We propose a method to model the wet etch process within the Shallow Trench Isolation (STI) module in the CMOS technology. To model a process is the first step in the design of a run to run system, in order to reduce for example the lot to lot variability (a lot equals 25 wafers). The developed predictive model is based on a Design Of Experiments (DOE).
Published in:
Advanced Semiconductor Manufacturing Conference (ASMC), 2011 22nd Annual IEEE/SEMI
Date of Conference: 16-18 May 2011
- Page(s):
- 1 - 6
- ISSN :
- 1078-8743
- Print ISBN:
- 978-1-61284-408-4
- INSPEC Accession Number:
- 12071561
- Conference Location :
- Saratoga Springs, NY
- Digital Object Identifier :
- 10.1109/ASMC.2011.5898188
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
