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Issues on short circuits in large on-chip power MOS-transistors using a modified checkerboard test structure

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3 Author(s)
C. Hess ; Inst. of Comput. Design, Karlsruhe Univ., Germany ; L. H. Weiland ; R. Bornefeld

To control random quality deviation of large on-chip power MOS-transistors, we have developed a modified checkerboard test structure. Using this structure, the complete chip area is divided into distinguishable subchips, each containing one large area power MOS-transistor. The fast digital measurements and the precise localization of transistor short circuits guarantee a fast process classification and enable additional electrical and optical defect parameter extraction

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997