Scheduled System Maintenance:
On May 6th, system maintenance will take place from 8:00 AM - 12:00 PM ET (12:00 - 16:00 UTC). During this time, there may be intermittent impact on performance. We apologize for the inconvenience.
By Topic

Design and characterization of SiGe TFT devices and process using Stanford's test chip design environment

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

The purchase and pricing options are temporarily unavailable. Please try again later.
5 Author(s)
Kumar, M.V. ; Center for Integrated Syst., Stanford Univ., CA, USA ; Subramanian, V. ; Saraswat, K.C. ; Plummer, J.D.
more authors

Stanford's test chip environment has been used to rapidly prototype a SiGe TFT process. The environment selected test structures tailored for the device/process. Then, with minimal effort and using parameterized test structures, the designer assembled a diagnostic test module. This module was used successfully in the development and optimization of the process, leading to the fabrication or high performance SiGe TFTs

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997