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Measurement and characterization of multi-layered interconnect capacitance for deep submicron VLSI technology

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7 Author(s)
Dae-Hyung Cho ; Adv. Device Phys. Lab., Hyundai Electron. Ind. Co., Kyungki, South Korea ; Man-Ho Seung ; Nam-Ho Kim ; Hun-Sup Park
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This paper presents the measurement and characterization of multi-layered interconnect capacitances for a 0.35 μm CMOS logic technology, which is becoming a critical circuit limitation to high performance VLSI design. To measure multi-layered capacitances of interconnect lines, test structures and the measurement methodology are presented. The measured interconnect capacitances were employed to evaluate and calibrate TCAD tools for the simulation of high-speed interconnect technologies

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997