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Digital test circuit design and optimization for AC hot-carrier reliability characterization and model calibration under realistic high frequency stress conditions

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13 Author(s)
W. Jiang ; Dept. of Electr. Eng. & Comput. Sci., MIT, Cambridge, MA, USA ; H. Le ; S. A. Kim ; J. E. Chung
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This study presents one of the first comprehensive examinations of key issues in designing hot-carrier reliability test circuits that can provide realistic stress voltage waveforms, allow access to the internal device nodes, and provide insight about circuit performance sensitivity to hot-carrier damage. New insights about previous test circuit designs are presented and additional new test circuit designs demonstrated. The inherent design trade-offs that exist between realistic waveform generation and internal device accessibility are analyzed and clarified. Recommendations for optimal test-circuit design for hot-carrier reliability characterization and model calibration are proposed

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997