By Topic

Yield prediction using calibrated critical area modelling

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Gaston, G.J. ; GEC Plessey Semicond., Plymouth, UK ; Allan, G.A.

This paper describes how critical area software can be used in the accurate prediction of the yield of ASIC designs. The approach is based on calculating the actual area of the design most sensitive to defects, rather than using the traditional methods of using die area to calculate the yield. An obstacle course test structure is used to calibrate the software tools, by extracting values for inter and intra layer defect densities. The tools are then used to predict yield improvements on designs which have been modified to improve process yield

Published in:

Microelectronic Test Structures, 1997. ICMTS 1997. Proceedings. IEEE International Conference on

Date of Conference:

17-20 Mar 1997