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Dual-Layer Adaptive Error Control for Network-on-Chip Links

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2 Author(s)
Qiaoyan Yu ; University of Rochester, Rochester, NY, USA ; Paul Ampadu

In this work, we present a new error control method to improve the energy efficiency and reliability of network-on-chip (NoC) links. The proposed method combines the error control coding (ECC) capabilities of the NoC's datalink and network layers to dynamically adjust the error control strength in variable noise conditions. Network-layer ECC is used in low noise conditions and error control strength is enhanced by adding datalink-layer ECC in high noise regions. To switch between the two ECC modes at runtime without interrupting normal operation, we propose a dual-layer cooperative error control protocol and its hardware-efficient implementation using the concept of product codes. Theoretical analyses of residual error rate and performance show the proposed method outperforms previous single-layer fixed and adaptive error control schemes. Compared to previous solutions, the proposed method reduces residual packet error rate by up to four orders of magnitude, achieves up to 72% energy reduction and improves average latency by up to 64%. The energy and latency reduction benefits are maintained as the routing path length and packet size increase, at the cost of a moderate increase in area overhead.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:20 ,  Issue: 7 )