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A Cyclic Vernier TDC for ADPLLs Synthesized From a Standard Cell Library

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2 Author(s)
Youngmin Park ; Univ. of Michigan, Ann Arbor, MI, USA ; Wentzloff, D.D.

This paper presents a cyclic Vernier time-to-digital converter (TDC) with digitally controlled oscillators (DCOs), targeted for a synthesizable all-digital phase locked loop (ADPLL). All functional blocks in the TDC are implemented with digital standard cells and placed-and-routed (P&R) by automatic design tools; thus, the TDC is portable and scalable to other process technologies. The effect of P&R mismatch is characterized in calibration mode, and utilized to achieve a minimum TDC resolution of 5.5 ps. The TDC was fabricated in a 65 nm CMOS process, and occupies 0.006 mm2.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:58 ,  Issue: 7 )