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COOL interconnect low power interconnection technology for scalable 3D LSI design

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12 Author(s)
Chacin, M. ; TOPS Syst. Corp., Tsukuba, Japan ; Uchida, H. ; Hagimoto, M. ; Miyazaki, T.
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3D multi-chip stacking is a promising technology poised to help combat the “memory wall” and the “power wall” in future multi-core processors. However, as technology scales and the chip sizes increase due to the number of transistors, interconnects have become a major performance bottleneck and a major source of power consumption for microprocessors. In this article, we introduce a TSV-based ultra-wide inter-chip connection technology that enables systems to have lower power consumption, higher scalability in its functionality and performance just by increasing the number/type of chips, allows to be manufactured with much more flexibility, and has a better cost/performance than conventional 2D SoC based designs.

Published in:

Cool Chips XIV, 2011 IEEE

Date of Conference:

20-22 April 2011