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Multi- V_{T} UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

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14 Author(s)
Noel, J.-P. ; Lab. d''Electron. et de Technol. de l''Inf., Commissariat a l''Energie Atomique, Grenoble, France ; Thomas, O. ; Jaud, M. ; Weber, O.
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This paper analyzes the potential of fully depleted silicon-on-insulator (FDSOI) technology as a multiple threshold voltage VT platform for digital circuits compatible with bulk complementary metal-oxide-semiconductor (CMOS). Various technology options, such as gate materials, buried oxide thickness, back plane doping type, and back biasing, were investigated in order to achieve a technology platform that offers at least three distinct VT options (high-VT, standard- VT, and low-VT ). The multi-VT technology platform highlighted in this paper was developed with standard CMOS circuit design constraints in mind; its compatibility in terms of design and power management techniques, as well as its superior performance with regard to bulk CMOS, are described. Finally, it is shown that a multi-VT technology platform based on two gate materials offers additional advantages as a competitive solution. The proposed approach enables excellent channel electrostatic control and low VT variability of the FDSOI process. The viability of the proposed concept has been studied through technology computer-aided design simulations and demonstrated through experimental measurements on 30-nm gate length devices.

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Electron Devices, IEEE Transactions on  (Volume:58 ,  Issue: 8 )