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Physical Synthesis with Clock-Network Optimization for Large Systems on Chips

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7 Author(s)

In traditional physical-synthesis methodologies, the placement of flip-flops and latches is problematic, especially for large systems on chips. A next-generation electronic-design-automation methodology improves timing closure through clock-network synthesis and placement of flip-flops and latches to avoid timing disruptions or immediately recover from them. When evaluated on large CPU designs, the methodology saw double-digit improvements in timing, wirelength, and area versus current technology.

Published in:

Micro, IEEE  (Volume:31 ,  Issue: 4 )