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Speed-path debug is a critical step in improving clock frequency of a design to meet the performance requirement. However, speed-path debug based on functional patterns can be very expensive. In this paper, we explore speed-path debug techniques based on at-speed scan test patterns. Enhancements are implemented to improve over an earlier proposed scan-based speed-path diagnosis algorithm. We further report the application results by applying the improved algorithm to a leading-edge high-performance microprocessor design.