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A low voltage SONOS nonvolatile semiconductor memory technology

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4 Author(s)
White, M.H. ; Dept. of Comput. Sci. & Electr. Eng., Lehigh Univ., Bethlehem, PA, USA ; Yang Yang ; Ansha Purwar ; French, M.L.

The triple-dielectric polysilicon-blocking oxide-silicon nitride-tunnel oxide-silicon (SONOS) structure is an attractive candidate for high density E2PROMs suitable for semiconductor disks and as a replacement for high-density dynamic random access memories (DRAMs). Low programming voltages (5 V) and high endurance (greater than 107 cycles) are possible in this multidielectric technology as the intermediate Si3N4 layer is scaled to thicknesses of 50 Å. The thin gate insulator and low programming voltage enable the scaling of the basic memory cell and associated complementary metal-oxide-semiconductor (CMOS) peripheral circuitry on the memory chip. A SONOS 1TC memory cell is proposed in a NOR architecture with a cell area of 6F2 where F is the technology feature size. A 0.20 μm feature size permits a 1TC area of 0.24 μm2 for advanced 1-Gb nonvolatile semiconductor memory chips. A physical model is presented to characterize the erase/write, retention and endurance properties of the nonvolatile semiconductor memory (NVSM) SONOS device

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Components, Packaging, and Manufacturing Technology, Part A, IEEE Transactions on  (Volume:20 ,  Issue: 2 )