Cart (Loading....) | Create Account
Close category search window

Consideration of thermal constraints during multichip module placement

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Man Chak Tang ; Dept. of Electr. & Comput. Eng., Arizona Univ., Tucson, AZ ; Carothers, J.D.

A multichip module placement algorithm which handles heat distribution as well as traditional placement objectives is presented. The algorithm uses a combined quad-partitioning genetic search, and simulated annealing technique. Experimental results show improvements in the min-cut and simulated annealing algorithms, in terms of net length, while satisfying the heat distribution constraints

Published in:

Electronics Letters  (Volume:33 ,  Issue: 12 )

Date of Publication:

5 Jun 1997

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.