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Overview of automatic defect classification

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3 Author(s)
M. H. Bennett ; SEMATECH, Austin, TX, USA ; K. W. Tobin ; S. S. Gleason

Summary form only given. It's no secret that ever-shrinking circuitry challenges all facets of integrated circuit (IC) processing. Lithography, clean-up, thin film, metallization, metrology, and inspection are all being pushed to accommodate smaller and smaller geometries. The same is true for particles, defects and microcontamination. As device sizes shrink, so does the size of particles or defects that cause chip failure and yield loss. Early particle detection and quick analysis are crucial to successful device fabrication. Unpatterned and patterned wafer defect detection is commonplace, and is accomplished at rapid speed and good sensitivity. However, the manual inspection, review and analysis of defects is a slow, labor intensive step that can be a critical bottleneck in the IC process. Automatic defect classification (ADC) is needed to improve inspection throughput and data integrity. ADC can provide enormous benefits; faster inspection/review, increased throughput, larger sample size, greater classification accuracy, improved classification reproducibility, reduced resource overhead, refocus of staff on troubleshooting and analysis, and reduced test wafer usage by utilizing product wafers. The most fundamental step in the design of an effective ADC system is in the translation of human experience and process knowledge into machine hardware and algorithms. For ADC, the key is developing image analysis algorithms that can be integrated or retrofit to existing defect detection/review tools. Ideally, ADC would be able to deal with both monochrome and color images from common imaging techniques used on defect detection and review tools

Published in:

Advanced Semiconductor Manufacturing Conference and Workshop. 1994 IEEE/SEMI

Date of Conference:

14-16 Nov 1994