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Observable time windows: verifying high-level synthesis results

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2 Author(s)
Bergamaschi, R. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Raje, S.

Verifying equivalence of the behavioral specification and scheduled implementation is a significant problem in high-level synthesis, because scheduling changes the cycle-by-cycle behavior. The authors present a practical method for comparing simulation results for the two using the same vectors

Published in:

Design & Test of Computers, IEEE  (Volume:14 ,  Issue: 2 )