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An efficient implementation of floating point multiplier

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3 Author(s)
Al-Ashrafy, M. ; Mentor Graphics, Cairo, Egypt ; Salem, A. ; Anis, W.

In this paper we describe an efficient implementation of an IEEE 754 single precision floating point multiplier targeted for Xilinx Virtex-5 FPGA. VHDL is used to implement a technology-independent pipelined design. The multiplier implementation handles the overflow and underflow cases. Rounding is not implemented to give more precision when using the multiplier in a Multiply and Accumulate (MAC) unit. With latency of three clock cycles the design achieves 301 MFLOPs. The multiplier was verified against Xilinx floating point multiplier core.

Published in:

Electronics, Communications and Photonics Conference (SIECPC), 2011 Saudi International

Date of Conference:

24-26 April 2011