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A 19–26 GHz balanced amplifier in 130 nm CMOS technology

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2 Author(s)
Shan He ; Department of Electrical and Computer Engineering, Queen's University, Kingston, Ontario, Canada ; Carlos Saavedra

The design of a fully integrated balanced amplifier implemented in a 130 nm CMOS technology is described in this paper. This balanced amplifier achieves a gain of 30 dB from 19 GHz to 26 GHz. To reduce the signal loss and the physical dimensions of the 90° coupler utilized in this balanced amplifier, a meandered broadside coupler with shield is designed. This on-chip 90° coupler occupies a compact area of 300 um × 120 um. An effective technique based on tuning the width of the transistors to achieve wideband operation is also proposed in this paper. The proposed balanced amplifier design achieves an IIP3 of -6.0 dBm and an input 1-dB gain compression point of -16.5 dBm. The OIP3 and the output 1-dB gain compression point are 24.0 dBm and 10.7 dBm, respectively.

Published in:

Sarnoff Symposium, 2011 34th IEEE

Date of Conference:

3-4 May 2011