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Error Tolerance in Server Class Processors

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5 Author(s)
Rivers, J.A. ; IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA ; Gupta, M.S. ; Shin, J. ; Kudva, P.N.
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This paper provides: 1) a very brief motivation and technological trend data to show why hard and soft errors are expected to be of increasing concern in the future; 2) a summary review of chip-level error tolerance practices today-with a brief reference to IBM's POWER6 and POWER7 designs; 3) open research challenges and current solution approaches of promise, based on published literature; and 4) concluding remarks.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:30 ,  Issue: 7 )