By Topic

Placement and Routing for Cross-Referencing Digital Microfluidic Biochips

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Zigang Xiao ; Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign, Urbana, IL, USA ; Evangeline F. Y. Young

Computer-aided design problems of digital microfluidic biochips are receiving much attention, and most of the previous works focus on direct-addressing biochips. In this paper, we solve the placement and droplet routing problem in cross-referencing biochips. In these biochips, the electrodes are addressed in a row-column manner, which may cause electrode interference that prevents simultaneous movements of multiple droplets. We propose a routing algorithm that solves the droplet routing problem directly. A two-coloring graph-theoretic method is used in our router to detect and prevent the electrode interference. In addition, we propose an integer linear programming based method to solve the placement problem. Our method considers the characteristics of cross-referencing biochips and is aware of droplet routing. Real-life benchmarks are used to evaluate the proposed methods. Compared with previous works, our router improves on average 4% in routing time and 58% in runtime. It can route all the benchmarks within the time limits, while the latest work fails in some cases. Moreover, experimental results show that by running our router on the placement result generated by our method and those generated by the latest work, an average improvement of 11%, 29%, 54%, and 46% in the maximum routing time, average routing time, stalling steps, and cell usage can be achieved.

Published in:

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  (Volume:30 ,  Issue: 7 )