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CMOS switched current phase-locked loop

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3 Author(s)
Leenaerts, D.M.W. ; Dept. of Electr. Eng., Tech. Univ. Eindhoven, Netherlands ; Persoon, G.G. ; Putter, B.M.

The authors present an integrated circuit realisation of a switched current phase-locked loop (PLL) in standard 2.4 μm CMOS technology. The centre frequency is tunable to 1 MHz at a clock frequency of 5.46 MHz. The PLL has a measured maximum phase error of 21 degrees. The chip consumes <2 mW from a 3.3 V power supply

Published in:

Circuits, Devices and Systems, IEE Proceedings -  (Volume:144 ,  Issue: 2 )