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As the NAND flash market demand for larger capacity with low cost increases, the feature-size scaling and multi-level per bit have been developed. In this paper, we present the newly adopted operation algorithms and their results such as intelligent ISPE(Incremental Step Pulse Erase), various biasing in grouped W/Ls and VNR(Virtual Negative Read) in TLC(Triple Level Cell) NAND flash.
Memory Workshop (IMW), 2011 3rd IEEE International
Date of Conference: 22-25 May 2011