Referenced Items are not available for this document.
As the NAND flash market demand for larger capacity with low cost increases, the feature-size scaling and multi-level per bit have been developed. In this paper, we present the newly adopted operation algorithms and their results such as intelligent ISPE(Incremental Step Pulse Erase), various biasing in grouped W/Ls and VNR(Virtual Negative Read) in TLC(Triple Level Cell) NAND flash.
Published in:
Memory Workshop (IMW), 2011 3rd IEEE International
Date of Conference: 22-25 May 2011
- Page(s):
- 1 - 2
- E-ISBN :
- 978-1-4577-0224-2
- Print ISBN:
- 978-1-4577-0225-9
- INSPEC Accession Number:
- 12061845
- Conference Location :
- Monterey, CA
- Digital Object Identifier :
- 10.1109/IMW.2011.5873234
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
