High Performance THANVaS Memories for MLC Charge Trap NAND Flash

In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO
₂
capping layer on top of the AI
₂
O
₃
blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TANOS with variable tunnel oxide thickness (TANVaS), respectively. It is found that HfO
₂
capping layer improves erase saturation level due to its better electron blocking capabilities during erase operation, as also confirmed by simulations. As a result of improved erase saturation, THANVaS device shows excellent performance of 9.5 V memory window with flat endurance up to 10
⁴
cycles and improved high temperature retention.