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High Performance THANVaS Memories for MLC Charge Trap NAND Flash

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9 Author(s)

In this paper we investigate THANOS and THANVaS memory devices featuring a 2 nm HfO2 capping layer on top of the AI2O3 blocking dielectric. Furthermore, we benchmark these devices against reference TANOS and TANOS with variable tunnel oxide thickness (TANVaS), respectively. It is found that HfO2 capping layer improves erase saturation level due to its better electron blocking capabilities during erase operation, as also confirmed by simulations. As a result of improved erase saturation, THANVaS device shows excellent performance of 9.5 V memory window with flat endurance up to 104 cycles and improved high temperature retention.

Published in:

Memory Workshop (IMW), 2011 3rd IEEE International

Date of Conference:

22-25 May 2011