By Topic

A Novel 3-D Vertical FG NAND Flash Memory Cell Arrays Using the Separated Sidewall Control Gate (S-SCG) for Highly Reliable MLC Operation

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Moon-Sik Seo ; Center for Interdiscipl. Res., Tohoku Univ., Sendai, Japan ; Bong-Hoon Lee ; Sung-Kye Park ; Endoh, T.

We propose a novel 3-dimensional (3-D) vertical floating gate (FG) type NAND flash memory cell arrays using the Separated - Sidewall Control Gate (S-SCG). This novel cell consists of one cylindrical FG with a line type control gate (CG) and S-SCG structure. For simplifying the process flow, we realized the common S-SCG lines by using the pre-stacked poly silicon layer, through which variable medium voltages are applied not only to control the electrically inverted S/D region but also to assist the program and erase operation. We successfully demonstrate the normal flash cell operation and show its superior performances in comparison with the conventional 3-D NAND cells by using the cylindrical 3-D device simulation. It is shown that the proposed cell can realize the highest CG coupling ratio, low voltage cell operation of program with 15V at Vth=4V and erase with 7V at Vth=-2V and good on/off read current margin by an order of over 1.5. Moreover, the proposed S-SCG cell array can fully suppress both the interference effects and the disturbance problems at the same time by removing the direct coupling effect in the same cell string, which are the most critical problems of the recent 3-D vertical stacked cell structures. Above all, the proposed cell array has good potential for Terabit 3-D vertical NAND flash cell array with highly reliable multi level cell (MLC) operation.

Published in:

Memory Workshop (IMW), 2011 3rd IEEE International

Date of Conference:

22-25 May 2011