By Topic

New Read Scheme of Variable Vpass-Read for Dual Control Gate with Surrounding Floating Gate (DC-SF) NAND Flash Cell

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
HyunSeung Yoo ; R&D Div., Hynix Semicond. Inc., Icheon, South Korea ; Eunseok Choi ; HanSoo Joo ; Gyuseog Cho
more authors

New read operation scheme has been proposed for three-dimensional (3D) Dual Control gate with Surrounding Floating gate (DC-SF) NAND flash memory [1]. Based on TCAD and analytic model, the selected cell threshold voltage (VT) is increased by high neighbor cell VT because neighbor cell does not have enough Vpass-read to be "pass-transistor" in conventional read operation. To prevent this neighbor cell high VT effect, higher Vpass-read is applied to control gate (CG) of neighbor cell. And lower Vpass-read is applied to CG of the next neighbor cell to compensate FG potential of neighbor cell. For read operation of multi level cell, Vpass-read modulation has to be decreased corresponding to the selected cell read voltage VR. By using new read scheme, a stable read operation is successfully achieved in DC-SF NAND flash cell for MLC (2bit/cell) and TLC (3bit/cell).

Published in:

Memory Workshop (IMW), 2011 3rd IEEE International

Date of Conference:

22-25 May 2011