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In this paper, a compact SRAM cell with low-power and stable operation is proposed using vertical MOSFET technology, and its impact on the cell size and the performance is examined. Although the proposed SRAM cell is composed of 12 transistors, it has a small cell size, which is only 74% of the conventional 8T-SRAM cell, because of its stacked vertical MOSFET structure. The proposed SRAM cell with vertical MOSFET realizes a reduced power dissipation during the write operation which is 47% and 44% of the conventional 6T and 8T SRAM cell, respectively. Furthermore, the proposed SRAM cell with vertical MOSFET has achieved 3 times larger write and read Static Noise Margin (SNM) than that of the conventional planar 6T or 8T-SRAM cell, and its SNM is more tolerant against threshold voltage (Vth) fluctuation.