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Extending planar device roadmap beyond node 20nm through ultra thin body technology

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1 Author(s)
Maleville, C. ; SOITEC, Bernin, France

There is consensus in the IC industry that fully depleted devices will be the solution to the increasing challenges of device scaling towards nodes 20nm and 15nm. Fully depleted (FD) devices with undoped channels eliminate the threshold voltage VT variability due to random dopant fluctuation (RDF) reducing the overall VT variability by over 60%. For a given power supply FD devices have superior short channel behavior, exhibit significant lower leakage Ioff compared to bulk devices. These FD advantages enable an efficient power-perfomance-area (ppa) optimization at lowest VDD (e.g. ~0.6V) which is not possible with a bulk device architecture without a significant performance and area penalty. FD devices can be planar or FinFETs. In both cases SOI substrates enable an industrial architecture of ultra thin body (UTB) devices. Planar UTB devices offer the benefits of FD behavior in conjunction with an evolutionary IC design approach but require a highly uniform SOI UTB layer. UTSOI is an industrially mature SOI substrate technology that offers a highly uniform SOI thickness layer with ±0.5nm (7 sigma) thickness uniformity. Smart Cut technology is here offering its unique advantages in integrating a thin BOX layer thru wafer bonding, while accessing atom level uniformities thru hydrogen implantation. Furthermore, SOI thickness and buried oxide (BOX) thickness are decoupled parameters and can be tuned to meet the requirements of any IC sub-32nm CMOS technology. UTSOI substrates can be produced in large volumes in existing multiple sources, then, FDSOI devices are able to offer the option of merging G and LP technology in a cost effective platform for a wide range of applications.

Published in:

VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on

Date of Conference:

25-27 April 2011