A full-fledged surface potential based compact model for cylindrical gate transistors replete with physical effects such as polysilicon gate depletion, mobility degradation, quantum mechanical effects, short channel effects, leakage currents, and parasitic resistances and capacitances etc. is presented. For the first time we present calibration results of such a model to a cylindrical gate technology that exhibits asymmetric i-v characteristics.
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VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on
Date of Conference: 25-27 April 2011