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Design challenges for high performance and power efficient graphics and mobile memory interfaces

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6 Author(s)
Wei, J. ; Rambus Inc., Sunnyvale, CA, USA ; Amirkhany, A. ; Chuck Yuan ; Leibowitz, B.
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Future generation graphics applications require more than 1TB/s memory bandwidth with a constant power budget as in today's systems. In contrast, future mobile applications require power optimized memory interfaces that can provide sufficient memory bandwidth on the order of 25GB/s. The difference in the optimization criteria results in different design challenges and consequently, different architectural and circuit-level design tradeoffs. In this paper, we compare two different memory interface design examples, one from each area operating at 16Gbps and 3.2Gbps per pin respectively, and highlight their major differences in terms of driver and receiver design, as well as clock generation and distribution. We will also discuss some of the problems facing future generations of memory interfaces that push the limits of performance and power efficiency.

Published in:

VLSI Technology, Systems and Applications (VLSI-TSA), 2011 International Symposium on

Date of Conference:

25-27 April 2011