Skip to Main Content
A highly manufacturable embedded DRAM technology at 40 nm node is presented. This report provides the characterization data of 128 Mbit embedded DRAM test vehicle fabricated by 40 nm eDRAM 200 MHz low power process. The test vehicle is composed of 32 macros and each macro unit is 4 Mb with configuration 32 k × 128 bits. The process is cost effective and compatible to our low power Logic core process with three additional critical masks to the base process. The DRAM memory cell consists of a high performance pass gate transistor and a metal-insulator-metal (MIM) storage capacitor with a cell size of 0.0583 um2 (<; 1/4 of SRAM 0.242 um2) and small macro size of 0.145 mm2 per Mega bits (Mb). The stacked cell capacitor is formed using low temperature processed high-k dielectrics to achieve sufficient storage capacitance in DRAM cell. Low cell device leakage below 20 fA/cell at 105°C with silicided node process coupled with the high-k storage capacitance. The macro design for random access speed can operate from 25 MHz to 200 MHz comparable to 6 T SRAM. It has built-in ECC parity generation and correction circuits with memory storage space used for storing parity bits. The characterization is based on 200 MHz, covering Vcc+/-15% at 125°C/ 105°C/ 25°C/ -40°C. Process corner skew includes core device corners TT/FS/SF/FF/SS and fast/slow cell device. Highly manufacturing yield of 128 Mb macro is achieved to demonstrate the maturity of technology. The excellent cosmic ray (neutron) soft error rate (SER) performance of less than 4 FITs/Mb is also achieved. The integration technologies can be applicable to the future embedded DRAM in 28 nm, 20 nm node and beyond.