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This paper presents measurements on a surface-channel charge-coupled device (CCD) with gates implemented using single-layer poly-silicon gates. The device was manufactured in a 0.18-μm pinned photodiode CMOS process available commercially from the United Microelectronics Corporation. The CCD was built with a field plate covering all gates as well as the space between them, which allows the potential in the gap between nonoverlapping gates to be manipulated. We present charge-transfer-efficiency (CTI) measurements performed at clock frequencies of 1 and 5 MHz, and at multiple background packet sizes and field-plate voltages. We further propose and apply a method for separating CTI in four-phase CCDs due to trapping from the inefficiency stemming from other phenomena. The measurements show a single-stage CTI value ranging from 1.7 × 10-4, with a moderate background charge and substantial field-plate voltage, to 0.007 at zero field-plate voltage and the highest background charge tested. The CTI can be reduced significantly (more than a factor of 10 in some cases) by applying a significant negative voltage at the field plate. This and the fact that only a minor part of the CTI can be attributed to trapping indicate that the performance of the device is limited by the presence of potential hollows in the gaps between the gates.