Referenced Items are not available for this document.
This paper presents an in-depth case study in high-performance asynchronous adder design. A recent method, called “speculative completion”, is used. This method uses single-rail bundled datapaths but also allows early completion. Five new dynamic designs are presented for Brent-Kung and Carry-Bypass adders. Furthermore, two new architectures are introduced, which target (i) small number addition, and (ii) hybrid operation. Initial SPICE simulation and statistical analysis show performance improvements up to 19% on random inputs and 14% on actual programs for 32-bit adders, and up to 29% on random inputs for 64-bit adders, over comparable synchronous designs
Published in:
Advanced Research in Asynchronous Circuits and Systems, 1997. Proceedings., Third International Symposium on
Date of Conference: 7-10 Apr 1997
- Page(s):
- 210 - 223
- Meeting Date :
- 07 Apr 1997-10 Apr 1997
- Print ISBN:
- 0-8186-7922-0
- INSPEC Accession Number:
- 5572993
- Conference Location :
- Eindhoven
- Digital Object Identifier :
- 10.1109/ASYNC.1997.587176
- Product Type:
- Conference Publications
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