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Simulation of Warpage During Fabrication of Printed Circuit Boards

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4 Author(s)
Sung-Won Kim ; Grad. Sch. of NID Fusion Technol., Seoul Nat. Univ. of Sci. & Technol., Seoul, South Korea ; Sang-Hyuk Lee ; Dae-Jin Kim ; Sun Kyoung Kim

This paper presents a simulation method for the warpage that take places after the patterning process of printed circuit boards. To conduct an efficient as well as realistic simulation, a nonlinear thermo-elasticity problem with cure kinetics is approximated to a linear one by adjusting the thermal loading condition, which is the processing temperature where the stress-free state is assumed. This paper proposes a method that can determine such temperature based on a simple experiment. Moreover, methods for geometric modeling and meshing with finite elements are also proposed. With the use of the contact boundary conditions, complex copper patterns and dielectric layers are separately meshed and joined later. An experimental system is built for adjusting the thermal loading and verifying the simulation results. The numerical results are compared with experimental data to examine the validity of the method.

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Components, Packaging and Manufacturing Technology, IEEE Transactions on  (Volume:1 ,  Issue: 6 )