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A 550- \mu\hbox {W} 10-b 40-MS/s SAR ADC With Multistep Addition-Only Digital Error Correction

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4 Author(s)
Sang-Hyun Cho ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea ; Chang-Kyo Lee ; Jong-Kee Kwon ; Seung-Tak Ryu

A speed-enhanced 10-b asynchronous SAR ADC with multistep addition-only digital error correction (ADEC) is presented with a straightforward DAC switching algorithm. The capacitor DAC is virtually divided into three sub-DACs for ADEC with negligible hardware overhead. The redundant decision cycles between stages reconfigure the capacitor connection of the DAC. These redundancies guarantee 10-b linearity under 4-b-accurate DAC settling in the MSB decision and the optimally designed ADC enhances the conversion speed by 37%. A prototype ADC was implemented in a CMOS 0.13-μm technology. The chip consumes 550 μW and achieves a 50.6-dB SNDR at 40 MS/s under a 1.2-V supply. The figure-of-merit (FOM) is 50 fJ/conversion-step.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:46 ,  Issue: 8 )

Date of Publication:

Aug. 2011

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