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A 622-MHz CMOS phase-locked loop with precharge-type phase frequency detector

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3 Author(s)
Notani, H. ; System Lsi Laboratory, Mitsubishi Electric Corporation ; Kondoh, H. ; Matsuda, Y.

A new approach to implement high-speed phase detector with precharge logic will be presented. The minimum detectable phase difference is 40 psec and is less than a half of conventional detector. A bias generator with complementary input stage is also developed to enhance the dynamic range of the VCO under low supply voltage. A fully CMOS phase-locked loop (PLL) was designed using 0.5-μm technology. By virtue of this simple fast detector and bias generator, 622-MHz stable operation was achieved by simulation.

Published in:

VLSI Circuits, 1994. Digest of Technical Papers., 1994 Symposium on

Date of Conference:

9-11 June 1994

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