CSD filter design for VLSI implementation of GA-VSB receiver

We present several filters for the Grand Alliance (GA) vestigial sideband (VSB) receiver. Especially, we design the digital filters for the digital frequency and phase lock loop (DFPLL), which can be easily integrated in a single VLSI chip, with limited bit length coefficients using canonic signed digit (CSD) code and evaluate the performance of the designed filters by comparing the frequency characteristics with the real coefficient filters. The CSD code conversion is a class of quantization in which the filter coefficients are quantized. A filter represented by a CSD code is called the CSD filter. The quantized coefficients which are restricted to the set of representable numbers by and digit CSD code with 2 nonzero digit (L=2, M=7) are considered. In spite of the simplified hardware (H/W) structure for implementation, it is shown that the CSD filters attain little difference compare to the case of real filters using real coefficients. When we select SEC STD60, the ASIC implementation of filters for the DFPLL using CSD filters requires about 30~35 K gates