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Experimental confirmation of an accurate CMOS gate delay model for gate oxide and voltage scaling

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4 Author(s)
Kai Chen ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Chenming Hu ; Peng Fang ; Gupta, A.

MOSFET's and CMOS ring oscillators with gate oxide thicknesses from 2.58 nm to 5.7 nm and effective channel lengths down to 0.21 μm have been studied at voltages from 1.5 V to 3.3 V. Physical and electrical measurement of gate oxide thicknesses are compared. Ring oscillators' load capacitance is characterized through dynamic current measurement. An accurate model of CMOS gate delay is compared with measurement data. It shows that the dependence of gate propagation delay on gate oxide, channel length, and voltage scaling can be predicted.

Published in:

Electron Device Letters, IEEE  (Volume:18 ,  Issue: 6 )